Around another 5 would experience junk on the character display over time where temperature shifts have affected the devices.This article will help you to determine the maximum acceptable difference between the baud rates of a UART transmitter and receiver.
![]() The interface lacks an external clock, and the Tx and Rx devices can reliably share data only when their internal baud rates are equal. In my experience, microcontrollers rarely offer an internal oscillator that has accuracy better than 1.5. Two microcontrollers with 1.5 clock sources will have baud rates that are different by as much as 3. ![]() If the receiver baud rate perfectly matches the transmitter baud rate and the first bit is sampled at the exact middle of the bit period, the last data bit will also be sampled at the exact middle of the bit period. In other words, the last data bit is the one that is most severely affected by baud rate discrepancy. Note: For convenience, well always assume that the Rx bit period is longer than the Tx bit period; the result would be the same if we assumed a shorter Rx bit period. I think a reasonable margin is 20i.e., the last bit must be sampled at least 20 of the bit period before the transition from last data bit to stop bit. So for an eight-data-bit interface, the sampling time for the last data bit will be off by 8T RX. In this section, well develop a comprehensive equation that can provide a more precise and customized estimate. As you can see from the following equation, M must be entered as a decimal, not a percentage. We need to change that because now the number of data bits (denoted by N) is a variable. We also will include a variable for the parity bit (P) and the stop bit (S). If you want to ensure that the stop bit is sampled correctly, use 1 for S; if not, use 0. The equation in its current form assumes 50 (i.e., the exact middle of the bit period). Any deviation from the ideal can cause the sampling position of later bits to be closer to the transition (and thus closer to an error). We will incorporate this into the equation by adding the following term to the left-hand side. So, for example, if the start bit is sampled 60 of the way through the bit period, this term would be (50 60)T RX 0.1T RX. You cant readily determine an exact value for this term, but if you know the details of your UARTs low-level functionality, you could come up with a reasonable worst-case estimate. Because different implementation will have different sensitivity to frequency shift. Naive implementation, something similar to considered in article (I have not seen examples). Implementation with 4x samples per bit, and with digital PLL-like system, which constantly monitors edges of bits and choose sample position nearest to center of bit. For example Zilogs UARTs uses this. ![]() I have put around 1000 systems into the field that use Atmel micros with their internal oscillator, which communicate with a display a few metres away via UART at 9600 baud. I have observed around 5 would fail outright because of baud rate mismatches, even with chips out of the same tubes.
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